cmrdm3590 surface mount dual n-channel enhancement-mode silicon mosfet description: the central semiconductor cmrdm3590 is an enhancement-mode dual n-channel mosfet, manufactured by the n-channel dmos process, designed for high speed pulsed amplifier and driver applications. this mosfet offers low r ds(on) and low threshold voltage. marking code: cr applications: ? load/power switches ? power supply converter circuits ? battery powered portable devices features: ? power dissipation: 125mw ? low package profile: 0.5mm (max) ? low r ds(on) ? low threshold voltage ? logic level compatible ? small sot-963 surface mount package maximum ratings: (t a =25c) symbol units drain-source voltage v ds 20 v gate-source voltage v gs 8.0 v continuous drain current (steady state) i d 160 ma continuous drain current, t p < 5.0s i d 200 ma power dissipation p d 125 mw operating and storage junction temperature t j , t stg -65 to +150 c thermal resistance ja 1000 c/w electrical characteristics per transistor: (t a =25c unless otherwise noted) symbol test conditions min typ max units i gssf , i gssr v gs =5.0v, v ds =0 100 na i dss v ds =5.0v, v gs =0 50 na i dss v ds =16v, v gs =0 100 na bv dss v gs =0, i d =250a 20 v v gs(th) v ds =v gs, i d =250a 0.4 1.0 v r ds(on) v gs =4.5v, i d =100ma 1.5 3.0 r ds(on) v gs =2.5v, i d =50ma 2.0 4.0 r ds(on) v gs =1.8v, i d =20ma 3.0 6.0 r ds(on) v gs =1.5v, i d =10ma 4.0 10 r ds(on) v gs =1.2v, i d =1.0ma 7.0 g fs v ds =5.0v, i d =125ma 1.3 s c rss v ds =15v, v gs =0, f=1.0mhz 2.2 pf c iss v ds =15v, v gs =0, f=1.0mhz 9.0 pf c oss v ds =15v, v gs =0, f=1.0mhz 3.0 pf q g(tot) v ds =10v, v gs =4.5v, i d =100ma 0.458 nc q gs v ds =10v, v gs =4.5v, i d =100ma 0.176 nc q gd v ds =10v, v gs =4.5v, i d =100ma 0.138 nc t on v dd =10v, v gs =4.5v, i d =200ma 25 ns t off v dd =10v, v gs =4.5v, i d =200ma 85 ns sot-963 case r5 (12-december 2012) www.centralsemi.com ? device is halogen free by design
cmrdm3590 surface mount dual n-channel enhancement-mode silicon mosfet sot-963 case - mechanical outline lead code: 1) source q1 2) gate q1 3) drain q2 4) source q2 5) gate q2 6) drain q1 marking code: cr pin configuration www.centralsemi.com r5 (12-december 2012)
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